Job Description
- The individual must be able to work intimately with advertising, Product definition, RTL plan, Physical Design, Verification, SW and Test groups and have the option to get a handle on innovations and undertaking needs rapidly, balance the needs, consistently and proactively draw in with the partners to complete things on time with the best quality and with insignificant supervision.
- The individual is additionally in charge of assessing/finishing outsider computerized and Analog IP(s) and incorporating the outsider IP with MBit SoC and furthermore should ready to make purchase/make suggestions on the key IP(s).
- The individual should ready to decide, indicate and assess the suitability of complex equipment highlights and structures and guarantees that product and equipment plans interface accurately.
- Should ready to make proposal on key plan exchange offs with elite/low-control IPs
- Should ready to recognize, break down and resolves sub-framework and additionally SoC configuration challenges and give engineering direction all through the plan procedure from idea through mass volume creation.
Employment Requirements:
- Least 10+ long stretches of involvement in structure and design involvement with spotlight on framework level exchange offs for complex SoC.
- Top to bottom information and involvement in complex SoC engineering, including CPU(s), DSP(s), high/moderate speed interchanges peripherals, memory interface, multi-space timing, transport and interconnect structures is an absolute necessity.
- Broad building learning of high information rate, elite and low inertness and low power SoC structure ideally in cutting edge CMOS advancements is an unquestionable requirement.
- Involvement in front-end ASIC/SoC configuration is fundamental.
- Capability in Verilog or VHDL is basic.
- Exhaustive information of most recent EDA devices for front end plan and amalgamation is an or more.
- Involvement in RTL configuration including configuration audits, RTL usage, blend and confirmation strategies, chip raise and lab approval is basic.
- Involvement in beginning time control estimation and structure improvement for ultra low power SoC arrangement is an or more.
- Requires incredible relational aptitudes with demonstrated capacity to work successfully in a quick paced condition. Ought to be a decent cooperative person with great relational abilities.
- Must have solid documentation aptitudes.
- Should have B.E. (Comparable) or M.E. (Identical) in Electronics and Communications Engineering or Electrical and Electronics Engineering.
Company Profile:
Salary: Not disclosed
Industry: Semiconductors, Electronics
Functional Area: Embedded / Chip Design
Role Category:
Employment Type: Full time
Keyskills
