Job Description
- Procure learning microarchitecture an ASIC unit by contemplating the determination and collaborating with the sensible structure group.
- Compose and play out the test plan in close participation with the consistent structure group.
- Create inclusion models and check conditions utilizing UVM-SystemVerilog/C++. Compose, keep up and distribute the confirmation detail.
- Screen, examine and investigate recreation mistakes.
- Screen and examine reproduction inclusion results to improve tests appropriately consequently accomplishing inclusion focuses on schedule.
- Produce a viable and reusable code crosswise over activities.
- Aptitudes and limits
- Inquisitive, requesting and thorough.
- Acing artice arranged programming.
- Learning of UVM confirmation approach (or comparable) and SystemVerilog/SystemC equipment check dialects
- Learning of Constraint-Random/Coverage-Driven confirmation conditions advancement in SystemVerilog/C ++ (drivers/screens, limitation arbitrary tests, checkers and self-checking models and inclusion models written in SystemVerilog-Covergrourp/SVA)
- Learning of recreation devices and inclusion database representation instruments
- Powerful in issues tackling by quickly distinguishing their underlying driver and creating patches or workarounds under tight planning limitations
Required least Education
- Ace/Engineer in Electronics
Company Profile:
Salary: Not disclosed
Industry: IT / Software
Functional Area: Quality control regulatory
Role Category:
Employment Type: Full time
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