Job Description
- Least 3 years of experience working of SV and UVM approach.
- The individual ought to have skill in verif env advancement, useful inclusion, code inclusion, testplan improvement, testcase composing and investigating.
- He/she should have lead a group of 5-6 engineers for a time of in any event 2 years in later past.
- Other expertise necessity:
- Structure Languages: Verilog (must)
- Scripting: shell, Perl (great to have)
- Universally useful dialects: C, C++. (great to have)
- Institutionalized Interfaces (catchphrases for inquiry):
Company Profile:
Salary: Not disclosed
Industry: Semiconductors, Electronics
Functional Area: Embedded / Chip Design
Role Category: Team Leader
Employment Type: Full time
Keyskills
